Characterization of the CMS Endcap Timing Layer readout chip prototype with charge injection

Abstract We present the characterization of a readout Application-Specific Integrated Circuit (ASIC) for CMS Endcap Timing Layer (ETL) High-Luminosity LHC upgrade with charge injection. The ASIC, named ETROC and developed in 65 nm CMOS technology, reads out 16× 16 pixel matrix Low-Gain Avalanche Detector (LGAD). jitter contribution from is required to be below 40 ps achieve 50 overall time resolution per hit. analog circuits consist preamplifier discriminator. handles LGAD signal most probable value around 15 fC. discriminator generates digital pulse, which provides Time-Of-Arrival (TOA, leading edge) Time-Over-Threshold (TOT, pulse width) information. prototype (ETROC0) that implements single channel has been evaluated circuits, measured discriminator's edge, better than larger fC sensor capacitance. walk resulting different heights can corrected using TOT measurement. distribution standard deviation 29 after time-walk correction At room temperature, preamplifier's power consumption 0.74 mW 1.53 low- high-power mode, respectively. 0.84 pixel. With ASIC alone or sensor, performances fulfill ETL's challenging requirements.